1. Field of the Disclosure
Generally, the present disclosure relates to the manufacture of semiconductor devices, and, more specifically, to various methods of patterning features that have differing widths.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein field effect transistors (NMOS and PMOS transistors) represent one important type of circuit element used in manufacturing such integrated circuit devices. A field effect transistor, irrespective of whether an NMOS transistor or a PMOS transistor is considered, typically comprises doped source and drain regions that are formed in a semiconducting substrate that are separated by a channel region. A gate insulation layer is positioned above the channel region and a conductive gate electrode is positioned above the gate insulation layer. By applying an appropriate voltage to the gate electrode, the channel region becomes conductive and current is allowed to flow from the source region to the drain region.
Numerous processing operations are performed in a very detailed sequence, or process flow, to form integrated circuit devices, e.g., deposition processes, etching processes, heating processes, masking operations, etc. In general, the formation of integrated circuit devices involves, among other things, the formation of various layers of material and patterning or removing portions of those layers of material to define a desired structure, such as a gate electrode, a sidewall spacer, etc. Device designers have been very successful in improving the electrical performance capabilities of transistor devices, primarily by reducing the size of or “scaling” various components of the transistor, such as the gate length of the transistors. In fact, device dimensions on modern day transistors have been reduced to the point where direct patterning of such features is very difficult using existing 193 nm based photolithography tools and technology. Thus, device designers have employed various techniques to pattern very small features. One such technique is generally known as a sidewall image transfer technique.
Device designers are under constant pressure to increase the operating speed and electrical performance of transistors and integrated circuit products that employ such transistors. Device designers are also under constant pressure to reduce the power consumed by an integrated circuit device during operation. This is particularly true for integrated circuit products that are intended for mobile applications, such as cell phones, laptop computers, etc. In general, all other things being equal, the smaller the gate length of a transistor, the faster will be its operating or switching speed. This increase in operating speed is not without “costs,” as, in general, devices with smaller gate lengths exhibit increased leakage current when the transistor device is in the “off” state, which results in relatively more power consumption for the smaller gate length devices.
Thus, in some applications, device designers design chips comprised of transistors having different gate lengths formed on the same semiconductor substrate. For example, in the logic circuits of an integrated circuit product where switching speed and high performance is paramount, an integrated circuit product may be designed so as to only use high-performance, relatively smaller gate length transistor devices in such logic circuits. However, in other regions of the integrated circuit product where switching speed is not as critical, e.g., input/output circuits, the product may be designed so as to use transistor devices having relatively larger gate lengths in an effort to reduce the overall power consumption of the integrated circuit product.
Manufacturing features, such as gate structures, that have different critical dimensions or widths, e.g., different gate lengths, on the same semiconductor chip is not without its problems. FIGS. 1A-1F depict one illustrative prior art technique of forming features having different widths using a sidewall image transfer technique. This technique may generally be referred to as an “additive” sidewall image transfer technique. FIG. 1A depicts a prior art device 10 and regions 12A, 12B of the same semiconductor substrate 12. As indicated, features having a first critical dimension (“CD1 Features”) will be formed above the region 12A while features having a second critical dimension (“CD2 Features”), that is different than the critical dimension of the CD1 Features, will be formed above the region 12B.
At the point of manufacture depicted in FIG. 1A, a layer of material 14 to be patterned, e.g., a layer of gate electrode material, and a hard mask material 16 have been formed above the substrate 12. Also depicted in FIG. 1A are a plurality of so-called mandrel structures 17 and a layer of spacer material 18 that has been deposited across the substrate 12 by performing a conformal deposition process. In one illustrative example, the layer of material 14 may be a layer of polysilicon, the hard mask material 16 may be a layer of silicon nitride, the mandrels 17 may be comprised of a material that may be selectively etched relative to the hard mask material 16, such as an amorphous silicon material, and the layer of spacer material 18 may be a layer of silicon dioxide. The mandrels 17 may be formed by depositing a layer of mandrel material and thereafter patterning the layer of mandrel material using known photolithography tools and techniques. The width of the mandrels 17 and the thickness of the layer of spacer material 18 may vary depending upon the particular application.
FIG. 1B depicts the device 10 after several process operations have been performed. First, a masking layer 20, such as a patterned photoresist mask, has been formed above the substrate 12 such that it covers the region 12A but leaves the region 12B exposed for further processing. Thereafter, a second layer spacer material 22 has been formed above the first layer of spacer material 18 but only in the region 12B where the CD2 Features will be formed. The layer of spacer material 22 was deposited by performing a conformal deposition process and it may be comprised of the same material as that of the layer of spacer material 18. The thickness of the layer of spacer material 22 may vary depending upon the particular application.
FIG. 1C depicts the device 10 after several process operations have been performed. First, the masking layer 20 was removed, thereby exposing both of the regions 12A, 12B for further processing. Second, an anisotropic etching process was performed to define spacers 18 adjacent the mandrels 17 above the first region 12A and the combination spacer 18/22 adjacent the mandrels 17 above the second region 12B.
Then, as shown in FIG. 1D, the mandrels 17 were removed by performing a selective etching process that leaves the spacers 18 and the combination spacers 18/22 to act as masks in a subsequent etching process that defines features in the hard mask material 16, i.e., to create a patterned hard mask layer that will be used in defining various features in the layer of material 14.
Next, as shown in FIG. 1E, an anisotropic etching process was performed on the hard mask material 16 through the mask layer comprised of the spacers 18 and the spacer combination 18/22 to thereby define a patterned hard mask layer 16A that will be used in defining various features in the layer of material 14.
FIG. 1F depicts the device 10 after the spacers 18 and the combination spacers 18/22 have been removed. Note that the features of the patterned hard mask layer 16A positioned above the first region 12A have a uniform spacing or pitch “P1”. In contrast, the features of the hard mask layer 16A that are positioned above the second region 12B do not exhibit such uniform spacing. More specifically, the features in the patterned mask layer above region 12B have a first pitch “P2” and a second pitch “P3” that are different from one another. Also note that the pitch P1 (for features above the first region 12A) is different from either of the regions P2 or P3. At the point of fabrication depicted in FIG. 1F, one or more etching processes may be performed through the patterned hard mask layer 16A so as to transfer features defined in the patterned hard mask layer 16A to the underlying layer of material 14. Accordingly, the features defined in the layer of material 14, e.g., gate structures, will ultimately exhibit the same pitch characteristics as are present in the patterned hard mask layer 16A. Note that, in the embodiment depicted in FIGS. 1A-1F, the CD2 Features (above the region 12B) have a larger critical dimension than do the CD1 Features (above the region 12A).
FIGS. 2A-2F depict another illustrative prior art technique of forming features having different widths using a sidewall image transfer technique. This technique may generally be referred to as a “subtractive” sidewall image transfer technique. FIG. 2A depicts a prior art device 10 and regions 12A, 12B of the same semiconductor substrate 12 where features having a first critical dimension (“CD1 Features”) will be formed above the region 12A while features having a second critical dimension (“CD2 Features”), that is different than the critical dimension of the CD1 Features, will be formed above the region 12B. The description of the material and components in FIGS. 1A-1F apply equally to FIGS. 2A-2F.
At the point of manufacture depicted in FIG. 2A, the layer of material 14 and the hard mask material 16 have been formed above the substrate 12. Also depicted in FIG. 2A are the mandrel structures 17 and the above-described layer of spacer material 18.
FIG. 2B depicts the device 10 after several process operations have been performed. First, the masking layer 20 was formed above the substrate 12 such that it covers the region 12A but leaves the region 12B exposed for further processing. Thereafter, a spacer-trimming etching process, e.g., an isotropic etching process, was performed on the layer of spacer material 18 positioned above the second region 12B so as to reduce the thickness of the layer of spacer material 18.
FIG. 2C depicts the device 10 after several process operations have been performed. First, the masking layer 20 was removed, thereby exposing both of the regions 12A, 12B for further processing. Second, an anisotropic etching process was performed to define spacers 18 adjacent the mandrels 17 above the first region 12A and the reduced-thickness spacers 18R adjacent the mandrels 17 above the second region 12B.
Then as shown in FIG. 2D, the mandrels 17 were removed by performing a selective etching process that leaves the spacers 18 and the reduced-thickness spacers 18R to act as masks in a subsequent etching process that defines features in the hard mask material 16, i.e., to create a patterned hard mask layer that will be used in defining various features in the layer of material 14.
Next, as shown in FIG. 2E, an anisotropic etching process was performed on the hard mask material 16 through the mask layer comprised of the spacers 18 and reduced-thickness spacers 18R to thereby define a patterned hard mask layer 16A that will be used in defining various features in the layer of material 14.
FIG. 2F depicts the device 10 after the spacers 18 and the reduced-thickness spacers 18R have been removed. Note that the features of the patterned hard mask layer 16A positioned above the first region 12A have a uniform spacing or pitch “P1”. In contrast, the features of the hard mask layer 16A that are positioned above the second region 12B do not exhibit such uniform spacing. More specifically, the features in the patterned mask layer above region 12B have a first pitch “P2” and a second pitch “P3” that are different from one another. Also note that the pitch P1 (for features above the first region 12A) is different from either of the regions P2 or P3. At the point of fabrication depicted in FIG. 2F, one or more etching processes may be performed through the patterned hard mask layer 16A so as to transfer features defined in the patterned hard mask layer 16A to the underlying layer of material 14. Accordingly, the features defined in the layer of material 14, e.g., gate structures, will ultimately exhibit the same pitch characteristics as are present in the patterned hard mask layer 16A shown in FIG. 2F. Note that, in this embodiment, the CD2 Features (above the region 12B) have a smaller critical dimension than do the CD1 Features (above the region 12A).
As noted above, in manufacturing modern integrated circuit products, the critical dimensions of various structures that are formed when manufacturing integrated circuit products have decreased to the point where it is very difficult to form such features so that they exhibit uniform characteristics. In both of the examples described above, the fact that the features formed in the layer of material have different pitches makes the fabrication of such features even more difficult. That is, when patterning line-type features, for example, more uniform results are obtained when the pitch between such features is uniform. Forming such line-type features that have a non-uniform pitch pattern tends to result in variations in, for example, the width of the line features in areas where the pitch pattern changes. Such variations in the features, e.g., gate structures, can lead to decreases in device performance.
The present disclosure is directed to various methods of patterning features that have differing widths, wherein the features may be part of an integrated circuit device.